Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and fabrication methods.
Flash memory devices have undergone rapid development. Flash memory devices can store data for a considerably long time without powering, and provide benefits such as high integration level, fast access, easy erasing, and rewriting. To further improve bit density and reduce cost of flash memory devices, 3D NAND memory devices have been developed to address the density limitation in planar memory cells.
A 3D NAND memory device can include a memory array and peripheral devices for controlling signals to and from the memory array. A 3D NAND memory device includes a stack of horizontal word lines arranged over a substrate, with a plurality of vertical memory strings formed through and intersecting the word lines into the substrate. Each memory string can include a vertical semiconductor channel, a tunnel oxide layer and a charge-trapping layer where the charge-trapping layer can trap or de-trap charges from the semiconductor channel or the word line. The intersection of a word line and a memory string forms a memory cell. For example, 32 word lines intersect a memory string and forms 32 memory cells, in series, along the memory string.
Each of the memory cells is operated by applying a voltage bias at the intersecting word line. During operations of a 3D NAND memory device, frequently applying bias voltage at the word line can disturb charge trapping in the charge-trapping layer. Consequently, threshold voltages of memory cells can be subject to undesirable disturbance which degrades reliability of 3D NAND memory devices.